Positions: Junior, Senior
Salary: Competitive salary with generous stock options
Commensurate with experience/skill
- This position is for a digital-SoC/ASIC design engineer to build next-gen analog/mixed-signal SoC chipsets.
- Handle several aspects of ASIC SoC design flow, which may include: MCU optimization, RTL coding, Verification, Synthesis, DFT, STA and P&R (for back-end design).
- Participate in chip debug, validation, and marketing specifications.
- BSEE with minimum 3-year experience or MSEE with minimum 1-year experience of digital experience.
- Highly desired is previous experience with MCU instantiation, on-chip memory optimization,
P&R, and programming (i.e. ARM Cortex-M0, RISC-V, MIPS).
- Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication), timing analysis, DFT, meta-stability, finite state machines.
- Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, integration/averaging, and decimation.
- Desired usage experience of mainsteam industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
- Experience in several vertical aspects of ASIC design (front-end and back-end P&R) will be a great plus.
- Experience in bus design (I2C, AHB/APB/AXI), datapath design (Filter, correlation or Cordic) and logic control (PCS or MAS) is a plus.
- Experience with CMOS image sensors (digital-design) such as MIPI, readout, and timing control, is a plus.
- Experience in metrics-driven verification methodology (System-Verilog/UVM based) is a plus.
- Experience in mixed-signal SOC design is a plus.
- Experience in perl/python/tcl scripts is a plus.