Positions: Junior, Senior
Salary: Competitive salary with generous stock options
Commensurate with experience/skill
1. This position is for a digital-ASIC verification engineer to build next-generation analog/mixed-signal SoCs.
2. Responsible for all aspects of UVM (Universal Verification Methodology), from start to finish. Good knowledge of communication protocols and associated verification IPs (VIPs). Extensive experience with assertions, cover properties, constrained random testing.
3. Developing verification automation scripts to improve verification efficiency.
4. Participate in chip debug, validation, and marketing specifications.
1. BSEE with minimum 3-year experience or MSEE with minimum 1-year experience of digital experience.
2. REQUIRED: Experience in metrics-driven verification methodology (System-Verilog/UVM based).
3. Strong scripting languages (Perl, Python, CShell, Makefile) experience.
4. Fundamental understanding of digital signal processing, such as FIR/IIR filter structure and decimation.